This relates to integrated circuits and, more particularly, to performing register retiming operations during implementation of an integrated circuit design.
Every transition from one technology node to the next technology node has resulted in smaller transistor geometries and thus potentially more functionality implemented per unit of integrated circuit area. Synchronous integrated circuits have further benefited from this development as evidenced by reduced interconnect and cell delays, which have led to performance increases.
To further increase the performance, solutions such as register retiming have been proposed, where registers are moved among portions of combinational logic, thereby achieving a more balanced distribution of delays between registers and thus potentially a higher clock frequency at which the integrated circuit may be operated.
However, performing register retiming before placement operations is based on an estimation of anticipated delays (i.e., the estimation is based on the number of combinational logic gates between registers in the pre-placement circuit design) and may lead to suboptimal register retiming solutions in terms of actual delays between registers.
Similarly, performing register retiming before routing operations is based on an estimation of anticipated delays (i.e., the estimation is based on the Manhattan distance between registers in the placed circuit design) and may lead to suboptimal register retiming solutions in terms of actual delays between registers caused by longer routes due to routing blockages.
Performing register retiming after placement or after routing operations may require an update of the previously determined placement solution or the previously determined placement and routing solution, respectively.